Beowulf: A theorical approach

Christoph Wasshuber wasshub at
Fri Jun 23 06:42:35 PDT 2000

I am trying a similar approach and would need help. I
do not have $2mil but some money is available to try
the following approach:

We are trying to design a motherboard which is a
'standard' motherboard but with an I/O interface
which directly plugs into the host interface bus
(between CPU and north bridge).

The motherboard is finished, the only thing which
remains is the host bus interface. We try to do a
simple I/O port (32 or 16 bit wide). Our goal is
to just listen in on the data and address busses
and snatch the appropriate data from the bus for
writing to the I/O port. For reading we try to
disable the northbridge and drive the data
bus. We hope to be able to do this with a high
speed FPGA. The main problems are in timing and
PCB layout.

If there are folks who would be willing to help in
the circuit design of this idea or to try the
DIMMS idea mentioned in earlier postings, please
contact me.

As I said, I am funding this myself, so there is not
a lot of cash available but enough to pay some
enthusiast for their hours of work spent during the
night :-)

Since this posting might appear as comming 'out of the blue'
here a very short paragraph about my intentions:

I am planing to design an affordable motherboard for Beowulfery
with a fast low latency network. The current plan is to
use the idea of PAPERS but scale it to 16, 32, or 64 bit
parallel with direct access to the CPU. Latencies of <100ns
should be possible. So the interface itself will be very
cheap because the hardware of PAPERS is trivial. Hooking this
up to the host bus, if possible with an FPGA, does not cost much
more than standard NICs today.
In case some think that designing a new motherboard is not
cost effective, I have several quotes for the layout and manufacturing
of such motherboards. Even with an initial prototype run of only
100 motherboards one could achieve a price of ~$150 per motherboard
for AMD K6 based design (only counting manufacturing and not design).

I am willing to fund such an effort. but I would need circuit designers
who are up to the challenge.


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