Beowulf: A theorical approach

Alvin Starr alvin at
Fri Jun 23 05:13:53 PDT 2000

On Thu, 22 Jun 2000, Robert G. Brown wrote:

> On Thu, 22 Jun 2000, Walter B. Ligon III wrote:
> > --------
> > 
> > Well, yeah, but its the PCI interface I'm talking about.  Robert Brown's
> > posting was really more to the point.  Build a NIC that interfaces
> > driectly to the CPU and memory.
> Sure, and memory is indeed another way to do it.  Build a small
> communications computer that "fits" into a memory chip slot.  I'd guess
> that one could make the actual interface a real (but small and very fast
> -- SRAM?) memory chip that was on TWO memory buses -- the one in the
> computer in question and on the "computer" built into the interface
> whose only function is to manage communications and which would be
> strictly responsible for avoiding timing collisions -- possibly with a
> harness that allows it to generate interrupts to help even more. (Can a
> memory chip per se generate trappable interrupts now? Don't know.) Then
> accompany it with a kernel module that maps those memory addresses into
> a dedicated interface space and manages the interrupts, so the CPU only
> tries to write the memory when it is writable and read when it is
> readable.

One other possiblity is to use videoram. They have row shifters and it is
possible to shift data into the ram and then load a whole row in a single
operation. The advantage is that the ram can be being used for other work
while the data is being shifted in. This can also be used as a very fast
method for initialzing chunks of the ram. Write a row of zeros and then
load them multiple times to get a zeroed page. I wonder how much CPU time
is spent just writing 0's to pages of memory?

Alvin Starr                   ||   voice: (416)585-9971
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