[vortex] 3c59x network driver question
Jonathan Lynch
jlynch at frink.nuigalway.ie
Fri Sep 23 20:08:21 PDT 2005
I have 3 network interface cards in a linux router using version 2.6.12 of the kernel. I use two
interface cards for incoming traffic and one for outgoing traffic. The two cards used for incoming
traffic, eth1 and eth2, are 3com network cards that use the 3c59x driver. The card that is used for
outgoing traffic uses the e1000 driver. The following is the output from /proc/interrupts and lspci.
CPU0
0: 299823889 XT-PIC timer
1: 173520 XT-PIC i8042
2: 0 XT-PIC cascade
5: 126665 XT-PIC Intel ICH5
8: 58667 XT-PIC rtc
9: 22162271 XT-PIC acpi, ehci_hcd:usb1, uhci_hcd:usb2, uhci_hcd:usb5,
i915 at pci:0000:00:02.0, eth2
10: 46703995 XT-PIC libata, uhci_hcd:usb4, eth0
11: 44809773 XT-PIC uhci_hcd:usb3, eth1
12: 4199807 XT-PIC i8042
14: 547056 XT-PIC ide0
15: 2696779 XT-PIC ide1
NMI: 0
ERR: 0
03:05.0 Ethernet controller: 3Com Corporation 3c905 100BaseTX [Boomerang]
03:07.0 Ethernet controller: 3Com Corporation 3c905 100BaseTX [Boomerang]
3:05.0 Class 0200: 10b7:9050
03:07.0 Class 0200: 10b7:9050
I loaded the module "options 3c59x debug=7,debug=7" in /etc/modprobe.conf to help me follow the
code. sample output from dmesg
boomerang_interrupt. status=0x8401
eth1: interrupt, status 8401, latency 5 ticks.
eth1: In interrupt loop, status 8401.
boomerang_interrupt->boomerang_rx
boomerang_rx(): status 8001
Receiving packet size 1514 status 85ea.
eth1: exiting interrupt, status 8000.
I have followed it up all the way to netif_rx() and have a few questions and would appreciate if
someone could answer them.
what does the register RxDComplete mean ?. The function boomerang_rx() loops on its value to take
packets of the rx ring buffer. Does this mean that while there are still packets in the rx ring the
interrupt handler will pass them up to upper layers ?
I have notcied that a lot of delay is introduced in the router due to the way packets from both
incoming interfaces end up in the output queue.
When there are two network interfaces mainly receiving packets and one mainly sending, will their
interrupt number affect how the order packets are put into the queue for transmission? Are
interrupts prioritised ie if packets arrive at both eth1 and eth2 at the same time, will the packets
from eth2 be passed to upper layers first because it has a lower interrupt number?
Are packets received from both network devices put into the same softnet queue for the 1 cpu?
Again, I would really appreciate if someone could answer my question.
Jonathan Lynch
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