[vortex] Mini PCI - no link

[Donald Becker]

On Fri, 21 Jun 2002, Dave Dribin wrote:

> I just tried the newest driver (v.099X), and ifconfig still reports
> the wrong MAC address.  Please let me know what I can do to help debug
> this.  Hello?  ... anyone home? :)

One of the reasons I released that version was to get known-working
changes out there before trying to fix this problem

Try the driver update, 0.99Xa, I've put in the test directory:
    ftp://ftp.scyld.com/pub/network/test/3c59x.c

________________
3c59x.c:v0.99Xa 6/21/2002

Added code to deduce the EEPROM command register layout and EEPROM table
format.
   Deal with 6 bit, contiguous 8 bit and discontiguous 8 bits address format
   Detect a table offset of 0x30 by looking for 0x6d50 at 0x37.

________________

> On Thu, Jun 20, 2002 at 04:44:36PM -0500, Dave Dribin wrote:
> > I've gathered some more info on my problem.  While using the test
> > vortext driver (v0.99W), the MAC address is incorrect:
..
> > However the vortex-diag tool reports it correctly:

So obviously I know how to read the EEPROM, I just don't implement that
knowledge in the driver.

> > Index #1: Found a 3c566 Laptop Tornado adapter at 0x1800.
> > EEPROM format 64x16, configuration table at offset 0x30:
> >     00: 2978 6056 0040 8060 0040 0000 0000 0080
> >       ...
> >   0x10: 0000 0000 0000 0000 0000 0000 10b7 6556
> >   0x18: 0000 0000 0000 0000 0000 0000 0000 0a0a
> >   0x20: ff29 2829 0008 0000 0000 0000 0000 0000
> >   0x28: 0000 ff01 0000 0000 0000 0000 0000 0000
> >   0x30: 0004 7651 2e9c 6056 0061 0009 0000 6d50
> >   0x38: 2970 0009 0004 7651 2e9c 0010 0000 00aa

This is the fourth of the three EEPROM cases anticipated.

You likely have an 8 bit EEPROM, with a chip that implements
discontiguous address bits, combined with a EEPROM format that put the
config table at offset 0x30.

The original EEPROM command register had the following bits:
   7:6  Operation (0x80 is read)
   5:0  Address
These bits are shifted out by the hardware to read the serial EEPROM.

When the first CardBus cards came out, the designers needed a larger
EEPROM to hold the CIS table.  So they put in a chip with 8 address bits
and ended up the (undocumented!) format
   9:8  Operation (0x200 is read)
   7:0  Address

Now normally a device driver controls an EEPROM by shifting out the bits
in software.  The operation is sent first, so a Read always starts with
bits '10...'.  The driver can figure out how many address bits the
EEPROM needs by watching to see when it starts to returns data.  Except
with the Vortex we don't know which bits to set to start a read, or when
we are seeing returned data!

A second set of designers, working on non-CardBus chips, decided they
needed to be backwards compatible.  So they implemented chips that did
  11:8  High address bits
   7:6  Operation (0x80 is read)
   5:0  Address

Good idea, with two flaws:
   It's ugly to split and shift the address bits
   We already had to deal with the non-compatible scheme.

To add in even more complexity, a new EEPROM format was added.  The
standard configuration table used to be at offset 0.   New fields were
added, and the table offset moved to offset 0x30.  So now not only do we
have to deal with diffent address bit layouts, we don't know where what
address we are supposed to read from!

-- 
Donald Becker				becker@scyld.com
Scyld Computing Corporation		http://www.scyld.com
410 Severn Ave. Suite 210		Second Generation Beowulf Clusters
Annapolis MD 21403			410-990-9993