21143-TD Bug found?!

[Donald Becker]

After another six hours this evening, I found the bug that has been keeping
the new 21143-TD CardBus cards from working.

The new 21143-TD chip fails when bit 24 "WIE" in CSR0 is set.
Setting this bit works on all earlier chips.

The precise symptom is that the bus master side of the chip hangs after
writing as little as a single word (four bytes) of the first received packet.
Host accesses (PCI slave access from the point of view of the 21143)
continue to work.
Transmitting packets, which requires writing only a single status word at a
time, does not cause a problem.

Arguably the WIE bit need not be set on x86 systems, and that is my proposed
fix.  Since current Intel processors are not very cache line oriented, equal
or perhaps very slightly better performance might be gotten by terminating a
write on any word boundary.  But this still seems to be a chip bug, and
performance will suffer on non-Intel/x86 systems.

>From the 21143 Hardware Reference Manual
____CSR0 bit 24   WIE  Write and Invalidate Enable____
When set, the 21143 supports the memory-write-and-invalidate command on the
PCI bus. The 21143 uses the memory-write-and-invalidate command while
writing full cache lines. While writing partial cache lines, the 21143 uses
the memory-write command. Descriptors are also written using the
memory-write command. When this field is reset, the memory-write command is
used for write access. This bit is effective only if CFCS<4> is set. 


[[ Any comment David?  Is there any CardBus bridge configuration or 21143
config space initialization that might be causing this problem? ]]

Donald Becker					  becker@cesdis.gsfc.nasa.gov
USRA-CESDIS, Center of Excellence in Space Data and Information Sciences.
Code 930.5, Goddard Space Flight Center,  Greenbelt, MD.  20771
301-286-0882	     http://cesdis.gsfc.nasa.gov/pub/people/becker/whoiam.html