[Beowulf] Intel combines Xeon and FPGA in a single socket

Joe Landman landman at scalableinformatics.com
Thu Jun 19 20:03:26 PDT 2014

On 06/19/2014 10:52 PM, Adam DeConinck wrote:
> Hash: SHA512
> This is interesting...
> http://www.theregister.co.uk/2014/06/18/intel_fpga_custom_chip/

This is what tensilica did previously though.  The issue that we had 
found playing with it (about a decade ago) was that the FPGA was too 
small to be useful for real computation.  You could run effectively toy 
problems on it, but not more than that.  Maybe this has changed 
significantly in the last decade, but I doubt it.  There is only a 
limited surface area per die and Xeon's are not small.

I think the idea is great, but the pragamatic issues are really hard.

Not to mention the programmability bit.

Seriously, I've always thought of generating some sort of domain 
specific set of instructions tightly coupled to a processor would be an 
awesome way to build an accelerated processor unit.  I've just not seen 
a big enough FPGA and enough support at the programming level to make 
this worth the effort.  But its intriguing.

Joseph Landman, Ph.D
Founder and CEO
Scalable Informatics, Inc.
email: landman at scalableinformatics.com
web  : http://scalableinformatics.com
twtr : @scalableinfo
phone: +1 734 786 8423 x121
cell : +1 734 612 4615

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