[Beowulf] Parallella funding goals were met

[Vincent Diepeveen]

Tim someone reported me it doesn't have a floating point  
multiplication unit.

Note that there is 50+ co processors like this around.

In the low power area with simple cpu's, the only thing that matters  
is the price
of producing it.

It is very common to buy SOC's and use a co processor for specific  
tasks.
For example for encryption.

The advantage of a co processor at such SOC's is that latency to it  
is fast
from the ARM/MIPS processor to the co processor.

So it's all about production price. If you just produce 1000-10k cpu's,
you can produce a FPGA prototype for say $50.

That's just the co processor price.

That's a high price and renders a CPU useless.

If you say however: "i want to produce it in 28 nm".
Then if you produce a few million of them, you can produce it for a  
small part
of that price. Maybe $5.

Now THEN you have an interesting co processor as it costs me only $5  
to put it in the SOC.

It's all about price in this industrial engineering area. Nothing  
else matters if you want to sell something there.

On Oct 31, 2012, at 4:23 AM, Tim Mattox wrote:

> Vincent,
> Each of the 16 processors on the chip has a single precision floating
> point unit,
> which includes multiplication.  What it doesn't have is 64-bit  
> floating point.
> And they already have samples at 28nm, so get off your high horse  
> and admit
> that you got this wrong.  It is a cool project and I look forward to
> seeing these
> boards next year.
>
> See page 36 of the epiphany_arch_reference_3.12.10.03.pdf found here:
> http://www.adapteva.com/support/docs/e3-reference-manual/
>
> Quoted here:
> "
> 7.1.4 Floating-Point Unit
> The floating-point unit (FPU) complies with the single precision
> floating point IEEE754
> standard, executes one floating-point instruction per clock cycle,
> supports round-to-nearest even
> and round-to-zero rounding modes, and supports floating-point
> exception handling. The
> operations performed are: addition, subtraction, fused multiply-add,
> fused multiply-subtract,
> fixed-to-float conversion, absolute, float-to-fixed conversion.
> Operands are read from the 64-entry register file and are written back
> to the register file at the
> end of the operation. No restrictions are placed on register usage.
> Regular floating-point
> operations such as floating-point multiply/add read two 32-bit
> registers and produce a 32-bit
> result. A fused multiply-add instruction takes three input operands
> and produces a single
> accumulated result. A large number of floating-point signal-processing
> algorithms use the
> multiply-accumulate operations, and for these applications the fused
> operations has the potential
> of reducing the number clock cycles significantly.
> "
>
> On Sat, Oct 27, 2012 at 6:02 AM, Vincent Diepeveen <diep at xs4all.nl>  
> wrote:
>> Not gonna be easy for him.
>>
>> Last time i checked producing a low volume low power chip in a couple
>> of thousands
>> it was $50 a chip.
>>
>> He'll have to deliver now a few thousands of ARM socs with such a co
>> processor for $99 a person
>> around may 2013, and the co processor must have at least 16  
>> processors.
>>
>> Then there is shipment costs and the ARM SOC costs.
>>
>> Now in Europe there would be VAT on top of the total amount as well,
>> making it tougher
>> to get the total costs at $99. In most nations VAT is just above 21%
>> going up to 25% in Eastern Europe.
>>
>> So there is going to be very little, if any, profit on this.
>>
>> At most a few dollars.
>>
>> All this for a co processor that's supposed to not have a
>> multiplication unit - so it can't comply to OpenCL.
>>
>> On Oct 27, 2012, at 10:48 AM, Eugen Leitl wrote:
>>
>>>
>>> Thanks to everybody who contributed!
>>>
>>> http://www.kickstarter.com/projects/adapteva/parallella-a-
>>> supercomputer-for-everyone
>>>
>>> 4,295
>>> Backers
>>> $782,862
>>> pledged of $750,000 goal
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>
>
> -- 
> Tim Mattox, Ph.D. - tmattox at gmail.com