[Beowulf] CPU Startup Combines CPU+DRAM?And A Whole Bunch Of Crazy

[Eugen Leitl]

On Mon, Jan 23, 2012 at 07:30:30PM -0500, Andrew Piskorski wrote:
> On Mon, Jan 23, 2012 at 03:50:09PM -0500, Rayson Ho wrote:
> 
> > http://iram.cs.berkeley.edu/
> > 
> > So 15 years later someone suddenly thinks that it is a good idea to
> > ship IRAM systems to real customers?? :-D
> 
> Sure.  But from when I last read about the IRAM stuff, I'm pretty sure
> it was strictly single core.  Their VIRAM1 chip had 13 MB of DRAM, 1
> cpu core, and 4 "vector lanes", with no mention of SMP or any sort of
> multi-chip parallelism at all.  If Venray has a good design for using
> hundreds or more IRAM-like chips in a parallel machine, that sounds
> like a significant step forward.  (The intended fab process and
> attendant design rules might also be quite different, although I'm not
> at all sure about that.)

In order to make best use of eDRAM it's best to organize
the CPU around the layout of the memory cells, treating it
as an array. You'll need a refresh register, best as wide
as possible, multi-kBit word sizes, add shifts (which helps
the network processor), VLIW/SIMD, large integer addition
and subtraction, and so on.

If you shrink the dies, use redunant connections to route
around dead dies you can have WSI with utilization rates
of >90% of the real estate. Even without FPUs such a sea
of nodes on a mesh maps very well to massively parallel
physical problems, AI (spiking neurons), and such. Even as
a particle swarm/game physics accelerator engine integrated
into RAM it really helps with massively boosting game
video and physics performance, with obvious applications in
GPGPU as well.

This is not at all stupid, if only this wouldn't be pushed
by apparent bozos.