[Beowulf] Optimal BIOS settings for Tyan K8SRE

Ivan Paganini ispmarin at gmail.com
Sun Sep 3 14:52:53 PDT 2006

Can you post what were the tweaking that you had undergone to access the
4GB?  Thank you.

On 8/31/06, stephen mulcahy <smulcahy at aplpi.com> wrote:
> Hi,
> I'm maintaining a 20-node cluster of Tyan K8SREs (4GB RAM, dual Opteron
> 270s) which are being used primarily for Oceanographic modelling (MPICH2
> running on Debian/Linux 2.6 kernel).
> I had to make some tweaks to make all 4GB of RAM visible to the OS.
> I'm now at the point where I'm considering a pass at performance tuning
> the system. Before I start on OS level tuning, I'm trying to figure out
> whether there are any performance improvements to be had from tweaking
> BIOS settings, particularly those relating to Memory and ECC. I have a
> reasonable conceptual understanding of what the various settings are doing
> (and have glanced at the AMD BIOS developers guide for reference) but I am
> very unclear on what the potential performance impact of any of these
> settings are. Does anyone have any general advice or pointers to good
> reference information on this?
> My current settings are,
> Hammer Configuration
>         HT-LDT Frequency        Auto
>         Dual-Core Enable        Enabled
>         ECC Features
>                 ECC     Enabled
>                 ECC Scrub Redirection   Enabled
>                 Dram ECC Scrub CTL      Disabled
>                 Chip-Kill       Disabled
>                 DCACHE ECC Scrub CTL    Disabled
>                 L2 ECC Scrub CTL        Disabled
>         Memory Hole
>                 4GB Memory Hole Adjust  Manual
>                 4GB Memory Hole Size    768 MB
>                 IOMMU   Enabled
>                 Size    32 MB
>                 Memhole mapping Hardware
>         Memory Config
>                 Swizzle Memory Banks    Enabled
>                 DDR clock jitter        Disabled
>                 DDR Data Transfer Rate  Auto
>                 Enable all memory clocks        Populated
>                 Controller config mode  Auto
>                 Timing config mode      Auto
>         AMD PowerNow!   Disabled
>         Node Memory Interleave  Auto
>         Dram Bank Interleave    Auto
>         GART Error Reporting    Disabled
>         MTRR Mapping    Discrete
> Any comments on those welcome.
> Thanks,
> -stephen
> --
>    Stephen Mulcahy    Applepie Solutions Ltd   http://www.aplpi.com
>   Unit 30, Industry Support Centre, GMIT, Dublin Rd, Galway, Ireland.
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Ivan S. P. Marin
Laboratório de Física Computacional
Instituto de Física de São Carlos - USP
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