[Beowulf] fast interconnects, HT 3.0 ...

[Richard Walsh]

Eugen Leitl wrote:
> In regards to keeping the wires short, does this IBM trick of keeping all
> wires equal-length work well on 3d lattices, and above? This would seem to
> be a must for those coming (hopefully) Hypertransport motherboards with 
> connectors.
>   
    Speaking of Hyper Transport 3.0 and its AC chassis-to-chassis 
capabilities and 10 to 20
    Gbps performance maximums one-way (non-coherent, off chassis I 
believe), what do the
    people that know say about scalability.  Are we looking at coherency 
within the board complex
    and basic reference ability off board or something else?

    Sounds like the Cray X1E pGAS memory model.  Is there a role for 
switches?  And then there is the
    its intersection with the  pGAS language extensions (UPC and CAF) 
... raising the prospect of
    much better performance in a commodity regime, with possible 
implications for MPI use.

    Anyone have a crystal ball or insights on this?

    rbw

-- 

Richard B. Walsh

Project Manager
Network Computing Services, Inc.
Army High Performance Computing Research Center (AHPCRC)
rbw at ahpcrc.org  |  612.337.3467

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