ATHLON vs XEON: number crunching

Greg Lindahl lindahl at
Thu Jun 20 15:18:09 PDT 2002

> >> Moreover, I am pretty that RDRAM actually has lower average latency 
> >> under load than SDRAM.
> >
> >No. It depends on the load. RAMBUS' problem has always been that it
> >>could raise bandwidth under ideal circumstances, but that its random
> >access latency was worse than normal memory. This has been true in
> >every RAMBUS generation.
> >
> >greg
> Mmm ... I think we are agreeing or perhaps you are distinguishing
> indirect addressing patterns from simple odd-stride ones.

I was disagreeing with your use of the word "average", actually.
Engineers like to compute average things, but real codes (and even
benchmarks) do not behave in a very average fashion, because the
distribution looks nothing like a gaussian. So your quote from the
rambus folks about "heavy load" is pretty much meaningless -- there
are a lot of ways to heavily load a memory subsystem, all different.

> Also, I note that both the McKinley/ZX1 from HP, EV7, and Cray SV2 will 
> use RDRAM. Would you argue that this is for bandwidth reasons only?

There are 2 major reasons: (1) pin count and (2) bandwidth.

With the EV7, they can cram a lot more memory busses on the chip (4)
due to the lower pin count, and the modestly higher per-bus bandwidth
limit is also a plus. If I recall correctly a RDRAM channel is just
over half the pincount of a DDR SDRAM channel.

Now if we want to get back to Beowulf, we care about cost, cost, cost,
bandwidth, and on-chip memory controllers giving lower latency,
probably in that order. The difference between on-chip and off-chip
latencies is much more important than the latency difference between
RDRAM and DDR SDRAM. Clawhammer will give you the first look at that
benefit; it's already in Transmeta & Power4.


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