ATHLON vs XEON: number crunching

[Richard Walsh]

On Thu, Thu, 20 Jun 2002 10:15:10 -0700: Greg Lindahl wrote:

>On Thu, Jun 20, 2002 at 09:15:21AM -0500, Richard Walsh wrote:
>
>> Moreover, I am pretty that RDRAM actually has lower average latency 
>> under load than SDRAM.
>
>No. It depends on the load. RAMBUS' problem has always been that it
>>could raise bandwidth under ideal circumstances, but that its random
>access latency was worse than normal memory. This has been true in
>every RAMBUS generation.
>
>greg

Mmm ... I think we are agreeing or perhaps you are distinguishing
indirect addressing patterns from simple odd-stride ones. Thought that 
RIMMs had alot more address lines offering more internal banks providing 
more fresh places to reference.  The time to deliver the address is
shorter also I believe because there are fewer lines to get out of
sync.

A quote from a technical document (somewhat Rambus biased and not
cover DDR) I have:

"Under heavy load conditions, the latency of SDRAM deteriorates
 rapidly. RDRAM holds up quite gracefully ... under heavy load,
 where memory performance is crucial to CPU performance, RDRAM
 has far lower latency than SDRAM."

Also, I note that both the McKinley/ZX1 from HP, EV7, and Cray SV2 will 
use RDRAM. Would you argue that this is for bandwidth reasons only?

Perhaps this is a total versus component latency difference?

rbw