[Beowulf] Rackable / SGI

Joe Landman landman at scalableinformatics.com
Fri Apr 3 17:24:57 PDT 2009

Glen Beane wrote:

> On Fri, Apr 03, 2009 at 08:47:42AM +0200, Eugen Leitl wrote:
>>  On Fri, Apr 03, 2009 at 07:34:26AM +0800, Stuart Midgley wrote:
>>  > In 2019 when Intel releases their 1024core chip, still at 2.5GHz with
>>  > 256GB dimm memory, a lot of people will be surprised that linux works
>>  Ain't going to work. Arguably doesn't work already beyond 8 cores
>>  in a single socket.
>>  Will have to do with embedded memory or stacked 3d memory a la
>>  http://www.cc.gatech.edu/~loh/Papers/isca2008-3Ddram.pdf
> We've been building bigger and bigger SMPs for a long time, making
> changes to improve the memory system as needed. How is multicore any
> different?

Now you have hierarchical busses, multi-level NUMA (with ScaleMP like 
things now that SGI has gone).

This isn't just a multi-level memory system, its multi-level memory 
system with a network and resources distributed over the network.

You have registers, local cache, local memory, remote memory ...

Basically todays machines are turning into, curiously enough, SGI Origin 
-like things.  Cache coherent with many cores over high speed/low 
latency networks.

You can close your eyes and pretend it is an SMP, but symmetry really 
isn't there apart from specific cases.

> memory bandwidth?  The number of cores on a single CPU is growing much 
> faster than the memory bandwidth to that CPU, right?

... which is why the chip vendors are going more memory controllers per 
CPU.  It wouldn't surprise me to see many serial memory controllers 
going forward.

Joseph Landman, Ph.D
Founder and CEO
Scalable Informatics LLC,
email: landman at scalableinformatics.com
web  : http://www.scalableinformatics.com
phone: +1 734 786 8423 x121
fax  : +1 866 888 3112
cell : +1 734 612 4615

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