FYI: superlinear speedups in GROMACS (fwd)
fraser5 at cox.net
Fri Mar 8 17:29:09 PST 2002
Don't the XEON chips have a meg or two of cache? I know they make some dual
XEON's motherboards...maybe even quad's...have a ball!
Also the P4's come 2X bigger L2 then the Xp's right?
IMO, any problem that fits on cache is too small and can probably be on
calculator. CFD is for real men... ;-) (just kidding)
From: beowulf-admin at beowulf.org [mailto:beowulf-admin at beowulf.org]On
Behalf Of W Bauske
Sent: Friday, March 08, 2002 8:14 PM
To: rfc822 Compliance issue To: added by system POTENTIAL SPAM
Cc: Beowulf at beowulf.org
Subject: Re: FYI: superlinear speedups in GROMACS (fwd)
Eugene Leitl wrote:
> On Fri, 8 Mar 2002, Dominic Wu wrote:
> > Would not a single CPU with a larger L2 cache solve the problem better
> Caches are very expensive due to chip yield reasons (bad die yield goes up
> exponentially with die size). In fact, it would make sense to drop cache
> from dies, and go for embedded memory instead, which also removes lots of
> other overhead, such as branch prediction and pipelining, plus allows to
> go to very broad on-die buses and hence naturally foster VLIW and SIMD.
That statement makes me curious. Do you mean embedded memory
on chip or what? If it's on chip, how is it any better than cache?
If not on chip, elaborate please on what you're describing.
I'd like to see a P4 with a GB or so of memory all on the chip.
Would make an interesting node for what I do.
Beowulf mailing list, Beowulf at beowulf.org
To change your subscription (digest mode or unsubscribe) visit
More information about the Beowulf