[vortex] RX overrun with 3COM 3c982

[Donald Becker]

On Thu, 14 Nov 2002, Claude Pignol wrote:
> Donald Becker wrote:
> >On Wed, 13 Nov 2002, Claude Pignol wrote:
> >
> >>>The only source for FIFO errors with this speicific chip is the errors
> >>>reported in Window 6 offset 5.
> >>>These errors can occur either because
> >>>  The chip ran out of PCI bandwidth
> >>>  The driver ran out of receive buffers, causing the PCI Rx transfers
> >>>  (the "upload engine") to stall.
> >>>
> >>>Are you running another high-bandwidth PCI device on the system?  Video
> >>>cards are the usual offenders.
...
> >>00:08.0 RAID bus controller: 3ware Inc 3ware ATA-RAID (rev 12)
> >
> >Hmmm, this might be doing long PCI bursts, not leaving enough for the
> >Ethernet.  If that's the case, the solution is to:
> >   Change the Min-grant / Max-Latency PCI settings
> >   Set the PCI bursts to much longer values, although the '982 has
> >     reasonable defaults.  The registers to change are the
> >     UpBurstThreshold at offset 0x3e and
> >     UpPriorityThreshold, offset 0x3c, default 4*32 = 128 bytes.
> >
> >You can read the maximum burst that actually happened at offset 0x7a
> >using vortex-diag.  I wouldn't change the UpPriorityThreshold except for
> >debugging -- 128 bytes is already a too-low value for whole-frame Rx bursts.
> >
> Well, I am little bit lost:
> Is offset 7a (windows 7 and 10th byte): it's always 0??

Not the windowed registers, but the directly accessed registers.

Oh, the external version of vortex-diag only shows up to offset 0x3f,
not all of the registers.  You can see some of these values by passing
the '-g' option.

I've just changed this in vortex-diag -- this will be in the next public
version.

> I don't know how to change the value of 0x3c
> and 0x3e. but before trying to change them it's a good thing to locate 
> them.


-- 
Donald Becker				becker@scyld.com
Scyld Computing Corporation		http://www.scyld.com
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