[vortex] Tyan Thunder K7 S2462 Dual 3c59x

[Bogdan Costescu]

On Wed, 16 Jan 2002, Donald Becker wrote:

> Since the driver doesn't know if the EEPROM uses 6 or 8 address bits, it
> determines the size by either trying to read a location and verifying
> the result, or sending out address bits and looking for the leading
> data marker bit.

Thank you for the explanation. It seems logical... but I don't really 
understand the code from vortex-diag which implements it, after an 
afternoon of comparing code and docs.

Firstly, for 905B, there are only 6 bits of address, so that's fine. For 
905C, there can be 2K, 4K and 16K chips (cf. docs), which means up to 10 
bits. However, page 81 of the 905C PDF says that bits 6 and 7 of the 
Command Reg are used for the command while higher order address bits are 
bits 8 to 11. There is also a paragraph just above the table that says 
something about legacy software functionality and some bit swapping: now I 
don't understand why they mean by this, as the "legacy" hardware didn't 
have more than 6 bits address space, so legacy software shouldn't be 
supposed to use more than 6 bits. If this table is correct, then the 
actual way of handling more than 6 bits in vortex-diag is incorrect, as 
the command should not be put as the 2 MSB, but always at bit 6 and 7.

Secondly, I don't understand the way of separating 6-bit and 8-bit ones 
(the "else" branch of the comparison with 0x5555). How can the second 
comparison (with 0xffff) tell this ?

> If the address size is incorrectly detected as 8 bits, the driver sends
> out 8 address bits and only the first six are used by the EEPROM.

OK, but if the detection mechanism is improved or the EEPROM size is 
somehow forced, data should be accesible (both read and write), right ?

-- 
Bogdan Costescu

IWR - Interdisziplinaeres Zentrum fuer Wissenschaftliches Rechnen
Universitaet Heidelberg, INF 368, D-69120 Heidelberg, GERMANY
Telephone: +49 6221 54 8869, Telefax: +49 6221 54 8868
E-mail: Bogdan.Costescu@IWR.Uni-Heidelberg.De