[vortex-bug] Tx int. mitigation

[Bogdan Costescu]

On Thu, 14 Dec 2000, Giuseppe Ciaccio wrote:

> My personal opinion is:  we do not really need Tx IRQ.

I was also thinking of something similar some months ago when I "fought"
against Donald about usefulness of both tx_full and tbusy... then I forgot
about it. 8-(

Let's call this sequence 1.
> 	if (there is "enough" room in the Tx ring) {
> 		/*  Most frequent case  */
> 		enqueue a packet;
> 		return(ok);
> 	}

2.
> 	/*  Apparently not "enough" room in Tx ring  */
> 	try to free the tail of Tx ring as much as you can;

3.
> 	if (there is room in the Tx ring) {
> 		enqueue a packet;
> 		return(ok);
> 	}

4.
> 	/*  Really no room in Tx ring: must wait  */
> 	if (dev->tbusy not set) {
> 		/*  Maybe bad news: start countdown...  */
> 		dev->trans_start = current time;
> 		set dev->tbusy;    /*  or something like that  */
> 		return(try again);
> 	}

5.
> 	/*  We were already waiting for Tx room...  */
> 	if (jiffies - dev->trans_start >= TX_TIMEOUT) {
> 		/*  Bad news!  */
> 		tx_timeout();
> 		return(error);
> 	}

Basically most of the code is already there, but in different places.

1. is trivial.

2. that's the most difficult part IMHO. You have to repeatedly check
DownListPtr in a fast-path. On solution is to use the DnComplete bit in
DPD's FSH, so the whole process is only reading at most TX_RING_SIZE times
from memory - but this works only for the cards that set this bit (Cyclone
and Tornado for sure, but older cards ?).
Another solution would be to not free the entire ring at once, but only,
say, half of it and the rest at the next Tx packet. This would imply
modification of step 1. to not return after enqueuing, but check if
the ring has more than one packet in it and try to free some.

3. is again trivial

4. and 5. I would put step 5 at the beginning of the sequence (along with
a test for tbusy), to allow fast return to upper levels (the way the
current drivers do). Then step 4 doesn't need the check for tbusy.

Sincerely,

Bogdan Costescu

IWR - Interdisziplinaeres Zentrum fuer Wissenschaftliches Rechnen
Universitaet Heidelberg, INF 368, D-69120 Heidelberg, GERMANY
Telephone: +49 6221 54 8869, Telefax: +49 6221 54 8868
E-mail: Bogdan.Costescu@IWR.Uni-Heidelberg.De