Mitigation and autonegotiation

[Bogdan Costescu]

On Thu, 20 Apr 2000, Andrew Morton wrote:

> Replying to myself again.  Sigh.
> 
> I've worked this one out.  If we clear TxIntrUploaded in the first leg
> of the 'if' then we'll only take an interrpt when _all_ packets have
> been uploaded, and there will be a tx gap while the CPU restarts the
> netif layer and starts to queue up more packets.  SO the original code
> is better: it'll generate an interrupt on the last-but-oneth queued
> packet, thus providing some interleaving. A little optimisation.

And also by "skipping" some interrupts, you increase the time between 2
Tx generated interrupts, which is bad for applications which fight for
lowest possible latency (M-VIA, etc.) Actually, I found good Mr. Becker's
ideea of enclosing TxIntrUploaded with a #ifdef interrupt_mitigation in
0.99L; this way, you only start to skip interrupts if you really want to
(and define this).

> > > Yes, I'm running full duplex. However, I had to modify both 0.99L and your
> > > driver to get this: set 3c905C as IS_CYCLONE|HAS_NWAY and then comment out
> > > one line in vortex_probe1:
> 
> I sent this suggestion through to a 905C owner who was having big
> autoneg problems.  His reply this morning stated with "Cool!".  Looks
> good.

I tried again today and I found out that commenting the line in
vortex_probe1() was not necessary; I don't remember what made me do it...
The full duplex capability is correctly identified based on the MII
registers in vortex_open() if dev->if_port == XCVR_NWAY.
So, only adding HAS_NWAY to 3c905C capabilities should do it.

Sincerely,

Bogdan Costescu

IWR - Interdisziplinaeres Zentrum fuer Wissenschaftliches Rechnen
Universitaet Heidelberg, INF 368, D-69120 Heidelberg, GERMANY
Telephone: +49 6221 54 8869, Telefax: +49 6221 54 8868
E-mail: Bogdan.Costescu@IWR.Uni-Heidelberg.De

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