FIX: 0.99L and timeouts

[Donald Becker]

On Thu, 20 Apr 2000, Andrew Morton wrote:
> Andrew Morton wrote:
> > 
> > I'm also wondering why we're not clearing TxIntrUploaded in prev_entry
> > for the other leg of the 'if' statement: where we're setting tx_full.
>
> I've worked this one out.  If we clear TxIntrUploaded in the first leg
> of the 'if' then we'll only take an interrpt when _all_ packets have
> been uploaded, and there will be a tx gap while the CPU restarts the
> netif layer and starts to queue up more packets.  SO the original code
> is better: it'll generate an interrupt on the last-but-oneth queued
> packet, thus providing some interleaving. A little optimisation.

Yes, the original code was carefully thought out.  I went through and spent
a lot of time looking at the timing, cache impact and PCI reference count of
the original code.  We used the 3c905 cards in P-100 and PPro-200 clusters,
and so I tuned for that hardware on 2.0.30 and early 2.2 kernels.

Many things have changed in the kernel and hardware since then, but the PCI
bus characteristics have remained pretty much the same so I expect that the
old tuning is still pretty reasonable.


Donald Becker				becker@scyld.com
Scyld Computing Corporation
410 Severn Ave. Suite 210
Annapolis MD 21403


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