0.99L and timeouts

[Bogdan Costescu]

On Mon, 10 Apr 2000, Andrew Morton wrote:

> The 3c59x specs can be obtained from
> http://support.3com.com/partners/developer/developer_form.html

Thank you for this! I thought that they are under NDA...

> hmmm...  It does write the address of the dirty_tx buffer to
> DownListPtr, which should trigger a transmit once the transmitter is
> unstalled.

Only if cur_tx - dirty_tx > 0, which is not true as they are equal!

> Well, cur_tx is the _next_ buffer to write to, and dirty_tx is the next
> one to send, so there are two pertinent states:
> 
> cur_tx = dirty_tx && tx_full = 0: No buffers queued
> cur_tx = dirty_tx && tx_full = 1: TX_RING_SIZE buffers queued.
> 
> So 'tx_full' changes the interpretation of 'cur_tx = dirty_tx'.

I beg to disagree here, IMHO cur_tx and dirty_tx are only incrementing
monotonically, while the ring is accesed through:

vp->dirty_tx % TX_RING_SIZE,
entry = vp->cur_tx % TX_RING_SIZE,
entry = vp->dirty_tx % TX_RING_SIZE,
prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE]
in different places.

So, when tx_full = 1, I expect that cur_tx = dirty_tx + TX_RING_SIZE. In
this case, (cur_tx % TX_RING_SIZE) = (dirty_tx % TX_RING_SIZE) is still
true.
However, I get cur_tx = dirty_tx which I interpret as ring empty (next
to be transmitted is an empty slot) and also as card's queue empty (as
dirty_tx is only incremented in vortex_interrupt if you don't get out of
the while loop on the DownComplete branch).

Then I ask again: why cur_tx = dirty_tx and tx_full = 1 ?

Also, I know that different architectures have different 'int' sizes, is
there any reason for dirty_tx and cur_tx to be architecture dependent (as
opossed to be u16, u32 or whatever)?

Sincerely,

Bogdan Costescu

IWR - Interdisziplinaeres Zentrum fuer Wissenschaftliches Rechnen
Universitaet Heidelberg, INF 368, D-69120 Heidelberg, GERMANY
Telephone: +49 6221 54 8869, Telefax: +49 6221 54 8868
E-mail: Bogdan.Costescu@IWR.Uni-Heidelberg.De

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