[tulip] Bug in tulip_interrupt?

Donald Becker becker@scyld.com
Tue Feb 19 19:26:00 2002

On Tue, 19 Feb 2002, Bhavesh P. Davda wrote:

> I think there is a bug in tulip_interrupt, where in if you get a TxIntr
> interrupt as indicated by CSR5, and if the status register indicated an
> error, the status register never gets cleared, and every frame
> transmitted after that using that ring buffer entry will be marked as a
> transmit error.

I think that you are mixing up two different concepts.

The TxIntr bit in the status register is clear early in the interrupt
dispatch loop.

	/* Acknowledge all of the current interrupt sources ASAP. */
	outl(csr5 & 0x0001ffff, ioaddr + CSR5);

> +                               /* Clear the status register */
> +                               tp->tx_ring[entry].status =
> cpu_to_le32(DescOwned);

The code you are proposing adding clears the descriptor error status
bit, and sets the DescOwned bit.  After one pass through the Tx ring,
the chip will loop retransmiting old packets as fast as the driver
handles the interrupts!

There is no need to clear the error status bit as the descriptor status
word is initialized when the Tx packet is queued.

	tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
	tp->tx_ring[entry].status = cpu_to_le32(DescOwned);

Donald Becker				becker@scyld.com
Scyld Computing Corporation		http://www.scyld.com
410 Severn Ave. Suite 210		Second Generation Beowulf Clusters
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