[tulip-bug] Re: patch avoids lockups under high load

[Josip Loncaric]

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Further research suggests that the PNIC chip simply does not have
TimerInt.  The only document I was able to find is dated 12/1994 and
gives preliminary information, but it says two important things about
PNIC:

(1) CSR11 is reserved
(2) CSR7 allows only 0x1b3ff as valid interrupts

Tulip.c:v0.92t considers link fail (0x1000) and link pass (0x10) as
invalid for PNIC (perhaps they are not used).  Perhaps the valid_intrs
setting for PNIC should be changed to 0x1a3ef (=0x1ebef & 0x1b3ff). 
Whenever a chip lacks TimerInt, tulip.c should never mask other
interrupts then rely on TimerInt for recovery.  I'm suggesting the
attached patch.

Sincerely,
Josip
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--- tulip.c-0.92t	Sat Feb  3 08:47:22 2001
+++ tulip.c	Sat Feb  3 09:07:05 2001
@@ -436,7 +436,7 @@
   { "Digital DS21143 Tulip", 128, 0x0801fbff,
 	HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_PWRDWN | HAS_NWAY
 	| HAS_INTR_MITIGATION, nway_timer },
-  { "Lite-On 82c168 PNIC", 256, 0x0001ebef,
+  { "Lite-On 82c168 PNIC", 256, 0x0001ebef & 0x0001b3ff,	/* PNIC lacks TimerInt */
 	HAS_MII | HAS_PNICNWAY, pnic_timer },
   { "Macronix 98713 PMAC", 128, 0x0001ebef,
 	HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer },
@@ -2827,7 +2827,7 @@
 				/* Josip Loncaric at ICASE did extensive experimentation
 				   to develop a good interrupt mitigation setting.*/
 				outl(0x8b240000, ioaddr + CSR11);
-			} else {
+			} else if (tulip_tbl[tp->chip_id].valid_intrs & TimerInt) {
 				/* Mask all interrupting sources, set timer to re-enable. */
 				outl(((~csr5) & 0x0001ebef) | AbnormalIntr | TimerInt,
 					 ioaddr + CSR7);

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