[eepro100] Slef Test Failed

[Donald Becker]

On Wed, 1 Feb 2006, aman-ul- haq wrote:

> i am working with eepro driver on mips processor with my out own
> manufactured PCI controller. we have been able to configure card get it's
> configuration space and read etc. When driver is loaded eeprom checksum
> is passed but self test is gets failed. When is dig it down to bit level
> i noticed there are two lines before self test in driver
>  
>                                     self_test_results[0] = 0;
>                                     self_test_results[1] = -1;
>  
> Now when
>                           outl(tx_ring_dma | PortSelfTest, ioaddr +
> SCBPort);
> statement is executed which i  think may be changing both 
> self_test_results[0] and  self_test_results[1] that is total of 8 bytes.

I think that you already know the answer here...

> But when i return from this statement STATUS register in my controller
> states that master abort has occured

...Which means a PCI transaction did not complete...

> and through debugger when i print
> the values of self_test_results[0] and  self_test_results[1]  then
>  
>                                     self_test_results[0] = 0x4f4518b;
>                                     self_test_results[1] = -1;
> which means that IO has been done on self_test_results[0] that now
> contains checksum but nothing has been done to self_test_results[1] ,
> that's why checksum fails.
> Is this the problem of my settings in controller register?

Almost certainly yes.  The chip did not complete one of the bus 
transactions.  The master abort confirms this.

> Is my
> controller is not dealing with multibyte transfers?

That would be my first guess.  But it also might not be completing a PCI 
bus transaction correctly.  Or there might be a 32/64 bit address or 
data transfer issue. 


-- 
Donald Becker				becker at scyld.com
Scyld Software	 			Scyld Beowulf cluster systems
914 Bay Ridge Road, Suite 220		www.scyld.com
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