[eepro100] Re: Transmitter Timeout -- addednum

Kallol Biswas kallol@bugula.fpk.hp.com
Mon, 31 Jul 2000 8:31:02 EDT

> If I understand right, you state that the hardware reads and caches the
> command from the (i+1)th slot when it proceeds (i)th even if (i)th descriptor
> has S bit in it, don't you?
> If it does so, it's a very broken piece!
> I don't know what documentation states about TX ring processing, but this
> policy clearly contradicts the common sense!

Why does it contradict common sense? The S bit does not stop prefeteching,
you could see it on a PCI logic analyzer. There are many I/O cards also
that use the same S bit policy, but those cards also support NOP command, you
don't have to put a NOP after each command but after evey cmd with S bit set.