[eepro100] i82559 w/o EPROM.

Bjorn Eriksson mdeans@algonet.se
Fri, 8 Dec 2000 15:30:12 +0100

Thanks for your help Donald,

> > > You will have to either add the EEPROM to your design, or modify
> > > the driver to hard-wire the transceiver and station address
> > > information.
> >
> >  I figured I'd look around some first before I hard-wire them
> > adresses this my self. Has anyone brought this up on the list
> > before? [I've downloaded and searched the archives w/o success.]
> The MAC address isn't really the problem.  You can use
>   ifconfig ... hw ether 00:11:22:33:44:55
> The unavailable issue is that the driver reads the transceiver type and
> MII address from the EEPROM, and without this info the driver
> will not work.

 Ok, I guess we'll buy 4096 addresses for $500 and use ifconfig for that.
I'm not sure about 'transceiver type' and 'MII address' though. [The term
'transceiver' doesn't appear in "GD82559ER Fast Ethernet PCI Controller"
data sheets - odd].

 Say we were to add a serial EPROM to our design, what values should we put
into it?

 Some quotes from the 82559ER pdf document:

<<The 82559ER is part of Intel's second generation family of fully
integrated 10BASE-T/100BASE-TX LAN solutions. The 82559ER consists of both
the Media Access Controller (MAC) and the physical layer (PHY) combined into
a single component solution. 82559 family members build on the basic
functionality of the 82558 and contain power management enhancements.>>

 and <<The 82559ER does not support external PHY devices and does not expose
its internal MII bus.>>

 and <<The 82559ER CSMA/CD unit implements both the IEEE 802.3 Ethernet 10
Mbps and IEEE
802.3u Fast Ethernet 100 Mbps standards. It performs all the CSMA/CD
protocol functions such as
transmission, reception, collision handling, etc. The 82559ER CSMA/CD unit
interfaces the
internal PHY unit through a standard Media Independent Interface (MII), as
specified by IEEE
802.3, Chapter 22. This is a 10/100 Mbps mode in which the data stream is
nibble-wide and the
serial clocks run at either 25 or 2.5 MHz.>>

 Some uninitiated guesswork on my part - could 'Primary interface chip' and
'Secondary interface chip' be:

MDI Register 2: PHY Identifier
15:0 PHY ID (high byte) Value: 02A8H
MDI Register 3: PHY Identifier
15:0 PHY ID (low byte)  Value: 0154H
>> [Que, 'byte'?]

 ? I.e 0x02A8 and 0x0154? Probably not :-/ It seems to me that only the 5
LSBits and the MSBit of phy[0] (read from eprom[6]) are used.

 Another uninitiated guess would be that this is 'PHY Address' in:

<<Management Data Interface Control Register
The Management Data Interface (MDI) Control register is a 32-bit field and
is used to read and
write bits from the MDI.

Bits  Description
31:30 These bits are reserved and should be set to 00b.
29    Interrupt Enable. When this bit is set to 1b by software,
      the 82559ER asserts an interrupt to indicate the end of
      an MDI cycle.
28    Ready. This bit is set to 1b by the 82559ER at the end
      of an MDI transaction. It should be reset to 0b by software
      at the same time the command is written.
27:26 Opcode. These bits define the opcode: 01 for MDI write and
      10 for MDI read. All other values (00 and 11) are reserved.
25:21 PHY Address. This field of bits contains the PHY address
      (Default = 00001b).
20:16 PHY Register Address. This field of bits contains the address
      of the PHY Register to be accessed.
>> (i.e I should use 0x0001 for sp->phy[0])

 but if these bits are available from the 'Control/Status Registers' why
should they be stored in non-volatile memory on-board?

> >  I'm a bit surprised to learn there are two addresses
> > associated with each MAC.
> I'm not certain what you mean by this.  Only 3Com has two slots for MAC
> ("station") addresses.  The first is the 3Com assigned permanent address.
> The second is the station address that is actually used, which is usually
> the same as the first.

 Ok, that was a misunderstanding on my part. I read "transceiver and station
address information" as meaning the MAC has two adresses.