[Beowulf] Mobos for portable use

[Lux, Jim (337C)]

On 1/20/17, 8:07 AM, "Beowulf on behalf of Lukasz Salwinski"
<beowulf-bounces at beowulf.org on behalf of lukasz at mbi.ucla.edu> wrote:

>On 01/19/2017 09:11 PM, Lux, Jim (337C) wrote:
>
>> On 1/19/17, 4:29 PM, "Beowulf on behalf of Lukasz Salwinski"
>> <beowulf-bounces at beowulf.org on behalf of lukasz at mbi.ucla.edu> wrote:
>>
>>> On 01/19/2017 02:09 PM, Lux, Jim (337C) wrote:
>>>
>>>>
>>>> -----Original Message-----
>>>> From: Beowulf [mailto:beowulf-bounces at beowulf.org] On Behalf Of Andrew
>>>> M.A. Cater
>>>> Sent: Thursday, January 19, 2017 12:49 PM
>>>> To: beowulf at beowulf.org
>>>> Subject: Re: [Beowulf] Mobos for portable use
>>> [...]
>>>> (I just found that at least a while ago, Xilinx supported clusters for
>>>> some of  their design tools.. Since right now the design I'm working
>>>> with takes an hour to synthesize (on a single machine), I'm going to
>>>> look further - it has been a real rate limiter in the lab, because it
>>>> makes the test, new design, load, test cycle a lot longer.)
>>>
>>> it looks like current (vivado 16.4) synthesis program hasn't been
>>> parallelized - it's strictly single threaded and so uses just one
>>> core... :o/  I've recently benchmarked a few i5 & i7 workstations
>>> - there seem to be very little differences (maybe 10-20%) between
>>> CPUs released over last ~4-5 years :o/
>>>
>>> lukasz
>>
>> yeah, on further investigation, the parallelized part is the iterative
>> ³try lots of options² which isn¹t much use.
>>
>> I¹ve got the design, I don¹t need to optimize a parameter.
>>
>
>to my knowledge, parts of place/route use more than one core. I'm
>guessing it might be because these were, from the very beginning, series
>of independent MonteCarlo-like runs that were easy to parallelize.
>

Makes sense.. way back in the 80s, their earliest tools used simulated
annealing for place and route (and it took all night on a 80286 based
computer, for a VERY small FPGA like the XC2064, back when folks were
looking to maybe, sometime, get down to micron feature sizes)… but schemes
like that are very amenable to parallelization.  They could easily run
multiple threads without having to spend a lot of software development
time.  Splitting it into multiple machines (i.e. a cluster) is a lot
harder, especially if their internal software architecture wasn’t set up
for that.

Surprising though.. given the number of people doing designs, and how long
it takes to run for not very complex designs on the latest parts
(something that would fill the largest Virtex 7 must take days), you’d
think that they’d work on it.  time is very much money.

Maybe that’s where folks like synopsys come in. You pay the big bucks for
the tools and it runs on that cluster.