[Beowulf] Intel Xeon E5-2600 v2

[Joshua Mora]

Sandybridge and Ivybridge do not have AVX2 extensions.
Haswell does.
Therefore SB and IB do 8DP FLOPs/clk/core 
HW does 16DP FLOPs/clk/core

AMD processors Interlagos,Abudhabi support FMA4 and FMA3/4 respectively. They
are capable as well of 8DP FLOPs/clk/core.

floating point operations in single precission is 2X double precission for
multicore architectures.

You should not guide your infrastructure investments on SP/DP FLOPs/clk/core
metric.
Better access temporarily it and run your own stuff.
Memory bandwidth and latency at the core and socket will correlate better on
real world workloads ( the part not related with I/O to NIC or storage).

Joshua
------ Original Message ------
Received: 10:18 AM PDT, 09/14/2013
From: Bruno Coutinho <coutinho at dcc.ufmg.br>
To: Roberto Ammendola <roberto.ammendola at roma2.infn.it>Cc: Beowulf Mailing
List <beowulf at beowulf.org>
Subject: Re: [Beowulf] Intel Xeon E5-2600 v2

> As far as I know a Ivy bridge core can do 16 SP operations/clycle and
> 8 DP ops/cycle using 256 bit FMA.
> 
> 2013/9/13 Roberto Ammendola <roberto.ammendola at roma2.infn.it>:
> > Hi list, does anyone know how many SP (and DP) operation per cycle per
> > core can perform an Intel Xeon E5-2600 V2family processor?Just for
> > counting peak GFLOPS...
> >
> > thanks a lot
> >
> > --
> > ______________________________________________________________________
> >
> >       Roberto Ammendola    INFN - Roma II - APE group
> > tel: +39-0672594504  email: roberto.ammendola at roma2.infn.it   // \
> >       Via della Ricerca Scientifica 1 - 00133 Roma             \\_/ //
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