[Beowulf] Are mobile processors ready for HPC?

Eugen Leitl eugen at leitl.org
Wed May 29 02:06:00 PDT 2013

On Tue, May 28, 2013 at 06:17:19PM +0000, Lux, Jim (337C) wrote:

> But I agree with Bogdan that raw processor speed doesn't necessarily imply scaleable power consumption, etc.

There seems to be a convergence in x86 (Haswell) and ARM core power efficiency recently.
> The enormous volumes of mobile devices does mean that whatever price you are getting those processors at is likely to be as low as it can be (that is, all the "economies of scale" have been fully realized).
> But, there's a significant "per chip" cost for handling, socketing, assembly, etc.  And that cost does not change very much with level of integration.  You get to the extreme where when you  buy7400 SSI parts (or, for that matter microcontrollers) that the dominant cost is the package: e.g. a 6 pin package is cheaper than an 8 pin package with the same exact die inside; and mounting the 8 pin package requires 33% more solder paste, and so forth.

The big point for SoCs, especially with stacked memory, is that there are fewer
solder pads. What is not present in COTS SoCs is signalling fabric, but that
is arguably not expensive in terms of Si real estate and pin count, if compared
to memory buses.
> That said, I think that these ideas are important to explore.. Slide 20 talks about the lack of ECC.   Well, if you're serious about exascale, you've got to embed fault tolerance into the very fabric of the algorithm, rather than trying to glue it on afterwards with ECC, or network retries, or whatever.

I wonder what happened to MRAM in embeddeds. Here's a fully static design
which takes no power or leaks, and is rad-proof to boot.

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