[Beowulf] Power calculations , double precision, ECC and power of APU's

Mark Hahn hahn at mcmaster.ca
Fri Mar 22 09:14:58 PDT 2013

> No ECC might be an issue.

Phi definitely has a mode to enable ECC for onboard dram,
similar to how Nvidia and AMD do it (somewhat reduced 
performance and capacity, since the interface is a power
of two bits wide.)  it says here:
that Phi has ECC on L2 as well.  (afaik it's fairly common
to do only parity on L1, especially for inclusive caches, 
since corrupted lines can be refetched from the L+1 cache.)

> Public information states approximately 2 SP
> ops per DP op. Sounds like the SIMD registers can do both, like a normal
> x86 chip.

Phi implements standard x86 integer, x87 (!), and the Phi-specific
512b-wide mode.  (I wish they'd just call it MMX512 or something, 
rather than inventing a new, inconsistent name.  MMX, SSE, SSE2, SSE3,
but then SSSE3, then back to SSE4, then AVX and now IMICPHIAVX++ ;)

although I'm excited to get my hands on a Phi, I can't help thinking
about how it seems a little rushed.  not supporting any of the *SSE*
levels, for instance.  I think the big question is whether Intel is 
going to put some impetus behind the product (piplineing multiple 
design teams, doing 2.5d integration, etc).  oddly, the only rumors
I hear about Phi futures are about sticking IB/etc on the board,
which seems like an unimportant detour to me unless it somehow manages
to produce unique levels of performance...

>> A dutch saying is: "whose bread you eat his word you speak"

your bread needs a pinch of salt.  or barrel.

regards, mark hahn.

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