[Beowulf] Is there really a need for Exascale?

[Eugen Leitl]

On Fri, Nov 30, 2012 at 12:24:56AM +0100, Einar Rustad wrote:

> Modern SRAM cells are normally 6 transistors per cell. DRAM is 1. An SRAM cell is a flip-flop and

Notice that MRAM is more like DRAM in terms of real estate,
and ST-MRAM at the right structure size switches as fast
as SRAM, takes as much energy as SRAM to switch, but needs no
refreshing nor leaks the way DRAM does, as it is fully static. 

> keeps the information as long as power is on.  The transistors should be as fast as possible; i.e. they 
> can be made in the same way as logic transistors.

Notice that in a hybrid stack you can address individual
dies in the stack, so you have some flexibility in
how you plan your access and refresh patterns. 

> DRAM stores the data in a capacitor. Leakage should be minimal and capacitance 
> relatively large to avoid too frequent refreshing. These characteristics are different from what is 
> needed to make fast logic and SRAM so combining processing and DRAM on the same die is problematic.
> I noticed the other day that IBM has made a new processor with embedded DRAM for a large L3 cache, 
> a move I find quite interesting for a general purpose processor.

It is very interesting. It is also possible to add a little
logic to DRAM, making it a lot smarter and utilizine ultrawide
on-die buses. That is much easier than adding a full CPU to
a DRAM, or vice versa, as it requires less layers and process
complexity.