[Beowulf] 3.79 TFlops sp, 0.95 TFlops dp, 264 TByte/s, 3 GByte , 198 W @ 500 EUR

Chris Samuel samuel at unimelb.edu.au
Tue Dec 27 04:04:02 PST 2011

On Fri, 23 Dec 2011 02:42:35 AM Prentice Bisbal wrote:

> At SC11, it was clear that everyone was looking for ways around the
> power wall. I saw 5 or 6 different booths touting the use of FPGAs
> for improved performance/efficiency. I don't remember there being
> a single FPGA booth in the past.

I couldn't be at SC'11 due to family health issues, but I'm sure I 
remember a number of FPGA booths at previous SC's.  I remember one at 
SC'07 or so that had FPGA's that would go into an AMD Opteron CPU 
socket for instance.

Ah yes, I even took a photo of it (the FPGA in the socket, not the 
booth I'm afraid) at SC'07:


Looks like an Altera FPGA.

   Christopher Samuel - Senior Systems Administrator
 VLSCI - Victorian Life Sciences Computation Initiative
 Email: samuel at unimelb.edu.au Phone: +61 (0)3 903 55545

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