[Beowulf] crunch per kilowatt: GPU vs. CPU

Bill Broadley bill at cse.ucdavis.edu
Mon May 18 12:51:38 PDT 2009

Lux, James P wrote:
> Going "off chip" (e.g. for a memory access) will increase energy
> consumption because you have to charge and discharge the capacitance of the PCB traces and
> drive the input impedance of the memory. This can be surprisingly large.
> Example: a typical load impedance on a SINGLE input pin is 10pF, and you
> swing 3.3V, so you are pushing 54.45E-12 joules to charge/discharge the
> capacitor. Do that 66 million times a second, on a bus 64 bits wide (don't
> forget the address bus as well), and it's about a quarter of a watt. Since
> there are typically some sort of series termination resistors or similar
> involved, the power dissipation in those terminations is comparable.  Now
> multiply that by several memory banks, long PCB traces, etc.

At SC, er, I'm guessing around 04 sun has some talks about on chip vs off
chip.  Something like a picowatt per bit for a calculation on chip and 1000
times that to get one bit off chip.  Their proposed solution to this was a
silicon to silicon interface.  Their system had 1/2 the chips would face down
and 1/2 the chips would face up.  There were two kinds of chips, memory and
cpu, which has an interface on each of the 4 edges.  They had some fancy
compensation for thermal expansion (or lack of), I think it might have
included some feedback for the cooling system.  They were claiming that in the
coming generations that power efficiency would be the dominate engineering
problem for HPC and that their solution was optimal for that case.

Has anyone heard about it since?

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