[Beowulf] Connectionists: NIPS workshop CfP: Parallel Implementations of Learning Algorithms

[Eugen Leitl]

----- Forwarded message from Dave_Touretzky at cs.cmu.edu -----

From: Dave_Touretzky at cs.cmu.edu
Date: Sun, 05 Oct 2008 00:34:08 -0400
To: connectionists at cs.cmu.edu
Subject: Connectionists: NIPS workshop CfP: Parallel Implementations of
	Learning Algorithms
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		  NIPS08 Workshop Call for Posters:

	   Parallel Implementations of Learning Algorithms:
		  What Have You Done For Me Lately?

Overview: Interest in parallel hardware concepts, including multicore,
specialized hardware, and multimachine, has recently increased as
researchers have looked to scale up their concepts to large, complex
models and large datasets.  In this workshop, a panel of invited
speakers will present results of investigations into hardware concepts
for accelerating a number of different learning and simulation
algorithms.  Additional contributions will be presented in poster
spotlights and a poster session at the end of the one-day workshop.

Our intent is to provide a broad survey of the space of hardware
approaches in order to capture the current state of activity in this
venerable domain of study.  Approaches to be covered include silicon,
FPGA, and supercomputer architectures, for applications such as
Bayesian network models of large and complex domains, simulations of
cortex and other brain structures, and large-scale probabilistic
algorithms.

Potential participants include researchers interested in accelerating
their algorithms to handle large datasets, and systems designers
providing such hardware solutions.  The oral presentations will
include plenty of time for questions and discussion, and the poster
session at the end of the workshop will afford further opportunities
for interaction among workshop participants.

Confirmed Speakers:

- David Andersen, Carnegie Mellon University
  Using a Fast Array of Wimpy Nodes.

- Michael Arnold, Salk Institute
  Multi-Scale Modeling in Neuroscience

- Dan Hammerstrom, Portland State University
  Nanoelectronics: The Original Positronic Matrix?

- Kenneth Rice, Clemson University
  A Neocortex-Inspired Cognitive Model on the Cray XD1

- Robert Thibadeau, Seagate Research
  When (And Why) Storage Devices Become Computers

- Additional speakers TBA.

Important Dates:
  October 31, 2008    Poster abstract submission deadline
  November 7, 2008    Notification of acceptance
  December 12 or 13   Workshop at NIPS

How To Submit:
  Algorithm developers, hardware developers, and researchers building
large-scale applications are all encouraged to present their work at the
workshop.  Send a brief abstract (one page should suffice) in any format
describing the approach and results you wish to present in poster form
at the meeting to.  David S. Touretzky, Carnegie Mellon University,
dst at cs.cmu.edu.  Submissions are due by October 31; decisions will be
announced by November 7.  Authors of accepted posters will be asked to
give a 2 minute spotlight presentation before the start of the poster
session.

Workshop Organizing Committee:
  Robert Thibadeau, Seagate Research
  Dan Hammerstrom, Portland State University
  David Touretzky, Carnegie Mellon University
  Tom Mitchell, Carnegie Mellon University

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