[Beowulf] Barcelona hardware error: how to detect

[Chris Samuel]

----- "Mark Hahn" <hahn at mcmaster.ca> wrote:

> the kernel patch was publicly distributed in dec 07.
> it appears to add some kernel logic to avoid the specific 
> L3 TLB states which don't behave correctly.  the bios-level
> workaround is different, and appears to disable the L3 TLB - 
> I don't know whether that actually disables the L3 itself...

I believe the patch re-enables the L3 cache and then
works around the problem in software.

When we were running B2 Barcelonas with this patch we
didn't hit the errata and didn't see the performance
penalty we would have expected if the L3 was disabled.

cheers,
Chris
-- 
Christopher Samuel - (03) 9925 4751 - Systems Manager
 The Victorian Partnership for Advanced Computing
 P.O. Box 201, Carlton South, VIC 3053, Australia
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