[Beowulf] Benchmark between Dell Poweredge 1950 And 1435

Bill Broadley bill at cse.ucdavis.edu
Mon Mar 12 10:12:47 PDT 2007

Robert G. Brown wrote:
> It's worth a small editorial insertion here that I "like" hypertransport
> for a variety of reasons -- perhaps because it is a packet-based
> internal network that makes your computer's CPU-memory architecture
> surprising like a cluster in miniature on the inside.  And just like any
> compute cluster, you need to tune your design choices towards your
> application.

I agree completely.  Sad that AMD doesn't play to their strength. 
Hypertransport had the potential for significant differentiation from
Intel solutions.  Currently it allows for dual sockets with somewhat
better memory performance that Intel's latest greatest dual FSB
woodcrest machines.  The story on quad socket shows a clear and
substantial advantage for hypertransport, but alas most of the market
isn't in quad sockets.

Seems like if AMD didn't get so stingy with the coherent HT links (which
only the 8xx chips usually have spare ports) that the market might generate
some really interesting opteron based solutions.

After all if pathscale can manage hypertransport -> IB, how much harder
would shared memory be..... if of course coherent HT worked at a reasonable

Or maybe if Nvidia can manage to build a low volume video card
with 768MB and a 80GB/sec memory system for $560 maybe some enterprising 
company could build a opteron based motherboard with amazing memory
bandwidth..... if of course coherent HT worked at a reasonable

Why shouldn't a video card be able to directly access all memory (and
vice versa)?

Then again maybe this is what AMD's torenza initiative is about

Seems like AMD stands to gain much more from the potential of
future coherent HT products then they do by losing $$$'s on lower
prices for the 8xx and 8xxx products vs the 2xx and 2xxxx products.

Not to mention if the world bought more quad socket machines that would
be a world that AMD would have a much larger lead in (because of
the onchip memory controller).

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