[Beowulf] torus versus (fat) tree topologies

Mark Hahn hahn at physics.mcmaster.ca
Tue Nov 16 16:07:02 PST 2004

> Mmm ... from your 2003 Hot Chips presentation on Elan 4 I see 231 
> nanos.  Which is right, or are we talking about two different things?

AFAICT, the 25ns figure is for an individual 8-port xbar chip,
and a full-sized switch is three stages of these.  but 6*25!=231.
I believe there's at least one quadrics doc that quotes 300ns for 
the switch.  perhaps the 231 number is derived from average latency
(since some ports are just one xbar away)?

also, isn't SGI's numalink network a dual fat-tree?  they're claiming
1.1 us latency these days (though again, that might be averaged over
all possible paths...)

regards, mark hahn.

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