[Beowulf] Vector processing on AMD 64

[Richard Walsh]

Art Edwards wrote:

>AMD has advertised that their 64 bit architectures have vector
>registers. This was initially very exciting because eigensolvers are not
>easily paralllized for medium-sized problems, but vectorize very well.
>I say this based on experience with the CRAY-YMP where we saw speed-ups
>ofrr 100 when we used a verctorized eigensolver. The Y-MP had, I think
>128 vector registers, which could easily account for the 100 speed up.

Vector computing on the microprocessor is almost a different beast
from traditional vector computing in that vectors are defined 
width-wise rather than length-wise.  As such the SSE1/2/3 offer
instructions that load, compute, and store either 4, 32 bit or 2, 64
entities at a time (not all micros load and store the full 128-bits). 

Unlike the Cray ISA, which loads words in sequence up to the vector 
length (64x64 or 128x64) from memory with a single instruction, the 
microprocessors load and computes on one wide word at a time (prefetching 
functions as a pseudo-vector load) ... that makes the vector length/
width of your microprocessor 2 or 4 depending on the word size.  The 
totality of the Cray ISA and architecture is only poorly emulated by 
the vector operations on the various "vectorizing" microprocessoers.

It is a good thing, but not very close to the original concept yet.

>Does anyone know?

>1. How many vector registers each of the AMD 64 bit CPU's has

    It has 16x128-bit regs, but these do not reflect vector 
    length. The Cray X1 has 32x64x64-bit regs per SSP.

>2. Is there a source for the old CRAY vector library?

    Not sure what is meant here, unless your are refering
    to SCILIB which is merely an API and can be emulated
    by any processor that can do FLOPS. Remember it is the
    ISA (and supporting hardware) that supports the libraries
    that is key. Someone may have written a SCILUB based on
    SSE instructions.

Regards,

rbw

PS Great to have the reflector operational again! 

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