FYI: Current SPECfp landscape...

Josip Loncaric josip at icase.edu
Thu May 10 14:41:30 PDT 2001


Greg Lindahl wrote:
> 
> On Thu, May 10, 2001 at 03:53:10PM -0400, Josip Loncaric wrote:
> 
> > The point is data compression: I can convey the first order
> > approximation in one number, with minor (<5%) errors.
> 
> You can? So when the Athlon comes out with a faster memory system,
> your answers break, or if the P4 gets a different chipset with a
> slower memory system, your answer breaks.

Sure.  But clearly we are talking about the *current* generation of high
performance memory systems.  There was no implication that this could be
extended to future technologies.  You are reading way more into this
than was actually said or implied.

Your point about ignoring memory bandwidth is puzzling.  Memory
bandwidth is very important to us, I am absolutely not ignoring it, I
merely consider it a *constant* for the purposes of this discussion. 
That constant is defined by the current state of the PC market.  This
was explicitly clear from my message.

The variables which *do* concern me in comparing P4/Athlon systems
[NOTE: see the chipset/memory specs in my previous message] are:

(1) Memory access patterns of our applications
(2) Compiler optimization capabilities for different architectures (this
includes SSE2 and prefetch instructions)

In summary, it is bad policy to consider everything as a variable at the
same time.  It is best to hold most things fixed, then compare a few
variables.  Also, one should never confuse a local model with a global
theory of everything.

BTW, it is interesting to note when the nature of a local model
changes.  This can tell you when to switch your attention to a new
limiting variable.

Sincerely,
Josip

P.S.  As we all know, frequency of improvements in memory and chipset
technology is not what it should be.  CPU speeds are changing much more
rapidly than memory speeds.  This is why building a balanced machine has
been so difficult lately, and why it makes sense to consider the current
state-of-the-art in memory technology a constant over our next
procurement cycle.

-- 
Dr. Josip Loncaric, Research Fellow               mailto:josip at icase.edu
ICASE, Mail Stop 132C           PGP key at http://www.icase.edu./~josip/
NASA Langley Research Center             mailto:j.loncaric at larc.nasa.gov
Hampton, VA 23681-2199, USA    Tel. +1 757 864-2192  Fax +1 757 864-6134




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