Aces' Hardware comparison of FPU performance (Athlon vs P4)

[Robert G. Brown]

On Fri, 29 Jun 2001, James Cownie wrote:

> Probably worth a look, if you're in the market for new nodes for FPU
> intensive work (the Intel compiler is available in beta on Linux,
> after all) :-
>
> http://www.aceshardware.com/Spades/read.php?article_id=40000189
>
> Fundamental conclusion is that the P4 flies when the compiler manages
> to use SSE2 vectorisation (and your code isn't bandwidth limited ;-)
> For "real" codes like SPECFP SSE2 doesn't win much.

By the way, filled with curiousity by some of the week's discussion I
browsed the gnu gcc development site and learned that:

  a) gcc 3.0 was released 6/8.  It will likely take a bit to see it out
in rpm form as it has to be carefully tested against the kernel
(obviously).

  b) gcc 3.1+ is out in beta, and has SSE 1&2.

I'm hoping/praying maybe going to have time to grab and build a copy and
rerun some benchmarks on Athlons with and without the SSE instructions.

In any event, the SSE issue is one whose days are clearly numbered.
Very shortly gcc will have full support in the mainline distribution.

   rgb

-- 
Robert G. Brown	                       http://www.phy.duke.edu/~rgb/
Duke University Dept. of Physics, Box 90305
Durham, N.C. 27708-0305
Phone: 1-919-660-2567  Fax: 919-660-2525     email:rgb at phy.duke.edu