Unisys

[Eugene Leitl]

On Fri, 23 Feb 2001, Alan Scheinine wrote:

> On the Tera CPU, the context switch is not costly whereas the CPU
> with leading-edge performance is costly.

I wasn't proposing fat CPUs. Tera CPU switches context every 
instruction, resulting in suboptimal single-thread performance.

Context switches are always costly, you either pay in latency or in
hardware (by having several instances of an engine). High-clock CPUs are
necessarily primitive, and memory bottleneck disappears with kBit wide
buses to embedded memory. Given low (essentially relativistical latency
constrained) messaging overhead, you can always lay out a pipeline
spatially across the wafer.