Mathematics of gigabit question

Patrick Geoffray patrick at
Fri Dec 7 14:38:43 PST 2001


Your post was a good guideline.
Two more things to keep in mind about PCI buses:

* PCI is a bus, that means you want to reduce the 
number of devices to the minimum if you want maximum 
performance. Each time you shared a PCI with something, 
you will of course give away some time on the PCI, but 
there will be a lot of PCI cycles wasted in arbitration.
Also, the PCI settings depend of the weakest devices on 
the bus: if you plug a SCSI controller supporting 64 bits 
and 33 MHz, your bus will be set at 33 MHz and everybody 
else will run at 33 MHz, even if the bus and another device 
can run at 66 MHz.

* There is some overhead in the PCI protocol, to get the right 
to speak on the bus or to tell the PCI chipset where the 
data you are goign to write will go for example.
This overhead is defined in PCI cycles. A 66 MHz bus will have 
2 times more cycles than a 33 MHz bus. The 64 bits/32 bits part 
is the size of the data transfered per cycle in burst mode,
64/33 is not the same things than 32/66. In a 66 MHz PCI bus, 
the overhead is smaller. 
PCI-X is a 64/100 PCI bus, plus some great features like 
interlaced transaction.

Motherboard vendors are not very interested in PCI performance, 
because the market of people able to max out a cheesy 32/33 PCI 
is tiny. Video was a killer application, but it was moved to a 
separated bus (AGP), mainly for marketing reason I think.


|   Patrick Geoffray, Ph.D.      patrick at 
|   Myricom, Inc.      
|   Cell:  865-389-8852          685 Emory Valley Rd (B)
|   Phone: 865-425-0978          Oak Ridge, TN 37830

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