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<p class="MsoNormal"><b><span style="font-size:12.0pt;color:black">From: </span></b><span style="font-size:12.0pt;color:black">Beowulf <beowulf-bounces@beowulf.org> on behalf of Joe Landman <joe.landman@gmail.com><br>
<b>Date: </b>Monday, June 21, 2021 at 6:46 AM<br>
<b>To: </b>Jonathan Engwall <engwalljonathanthereal@gmail.com><br>
<b>Cc: </b>"beowulf@beowulf.org" <beowulf@beowulf.org><br>
<b>Subject: </b>[EXTERNAL] Re: [Beowulf] AMD and AVX512<o:p></o:p></span></p>
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<p class="MsoNormal">On 6/21/21 9:20 AM, Jonathan Engwall wrote:<o:p></o:p></p>
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<p class="MsoNormal">I have followed this thinking "square peg, round hole." <o:p>
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<p class="MsoNormal">You have got it again, Joe. Compilers are your problem.<o:p></o:p></p>
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<p><snip discussion of architecture><o:p></o:p></p>
<p>To date, I don’t know that *<b>compilers</b>* pay much attention to things like IO (that’s buried in some library call no doubt).<o:p></o:p></p>
<p>>>Maybe, someday, we'll get a great HPC compiler for C/Fortran.<o:p></o:p></p>
<pre>Wasn’t the Fortran compiler for the 7600 highly optimized? Did vector unrolling and all that. And those compilers for the FPS boxes?<o:p></o:p></pre>
<pre><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"><o:p> </o:p></span></pre>
<pre><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">I think you mean great HPC compilers for chips that are available and fast <grin><o:p></o:p></span></pre>
<pre><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"><o:p> </o:p></span></pre>
<pre><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">I think, too that the comments about ARM vs x86 vs whatever are interesting.<o:p></o:p></span></pre>
<pre><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"><o:p> </o:p></span></pre>
<pre><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">We’ve moved a long way from clusters where the ethernet interconnect was rate limiting, and the nodes were single core, single memory, single disk (if any). When you start getting into processors with hundreds of cores, or you start looking at “nanojoules/instruction” (or is instruction even the right thing to be counting.. maybe it’s nanojoules/data operation – where that could be a read/write from memory, disk, or interprocessor link).<o:p></o:p></span></pre>
<pre><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"><o:p> </o:p></span></pre>
<pre><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">Look at the (probably) specious claim that Tesla has the 5<sup>th</sup> fastest supercomputer - articles are very light on details, but I think it’s a whole bunch of GPUs – but their “number of cores” isn’t very big compared to even #100 on the “Top 500” list.<o:p></o:p></span></pre>
<pre><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"><o:p> </o:p></span></pre>
<pre><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">However, it might well be that for Tesla’s specific processing load, that 5000 GPU cores *<b>is</b>* faster than most Top 500 clustes.<br><br>And, given the recent news about miners consuming all those joules – maybe our metrics should be looking at more than raw speed.<br><br>Jim<o:p></o:p></span></pre>
<pre><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"><o:p> </o:p></span></pre>
<pre><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">(who has not just 1, but TWO, ARM based clusters on the shelf behind his desk.. Yes, Beaglebones, but it’s an ARM, it’s 4 nodes, and I use various cluster tools to manipulate them – the connection fabric for one is kind of slow (802.11))<o:p></o:p></span></pre>
<pre><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"><o:p> </o:p></span></pre>
<pre><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"><o:p> </o:p></span></pre>
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