<div dir="ltr"><div>In a partial answer to my own question it looks like Likwid can count Issued versus Retired instructions <a href="https://github.com/RRZE-HPC/likwid/wiki/TutorialStart">https://github.com/RRZE-HPC/likwid/wiki/TutorialStart</a></div><div><br></div><div><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On 17 July 2018 at 10:10, John Hearns <span dir="ltr"><<a href="mailto:hearnsj@googlemail.com" target="_blank">hearnsj@googlemail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div>I guess I am not going to explain myself very clearly here. Maybe I wont make a coherent point.</div><div>I think I read on The Next Platform at the time a comment along the lines of - "as CPU Mhz speeds cannot continue to rise,</div><div>smart engineers who design CPUs have had to come up with mechanisms to increase performance continually, in the face of software developers who will not modernise their code."</div><div>Indeed of course we all run a huge base of legacy codes, and these will nto be retired any time soon.</div><div>So speculative execution is one mechanism to 'save the bacon' of users wanting more and more performance.</div><div><br></div><div>We in Beowulfery have taken advantahe of general purpose CPUs. Indeed, with CPUs themselves having wide vector units and several units per package (AMD) they actual CPU package looks like a supercomputer of old.</div><div>I digress. The big companies produce CPUS for the datacentre market, which is of course their biggest market. I get the impression that HPC is no small market either, and CPU varieties are engineered specifically for the HPC market.</div><div>To be clear, my argument is NOT that HPC is some sort of leftover from the data centre market - indeed it is a prime and growing market.<br></div><div><br></div><div>However, in the past there were specific architectures and instruction sets for supercomputing. What I am going to throw out to the floor is:</div><div><br></div><div>* The IT industry goes round in cycles. Is the time right for HPC specific processors again? <br></div><div><br></div><div>* Yes, you would need a Linux kernel and distribution ported to that CPU instruction set</div><div><br></div><div>* Regarding compiler technology, how important is speculative execution for HPC style codes?</div><div><br></div><div>* For the point above, can anyone point to studies where retired instructions versus unused have been counted for HPC codes? <a href="https://software.intel.com/en-us/vtune-amplifier-help-instructions-retired-event" target="_blank">https://software.intel.com/en-<wbr>us/vtune-amplifier-help-<wbr>instructions-retired-event</a><br></div><div><br></div><div>* What would HPC specific processors look like? Would they have speculative execution? What else would be missing - or added?<br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div><div><br></div></div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><div class="gmail_quote">On 17 July 2018 at 09:33, Chris Samuel <span dir="ltr"><<a href="mailto:chris@csamuel.org" target="_blank">chris@csamuel.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span>On Tuesday, 17 July 2018 11:08:42 AM AEST Chris Samuel wrote:<br>
<br>
> Currently these new vulnerabilities are demonstrated on Intel & ARM, it will<br>
> be interesting to see if AMD is also vulnerable (I would guess so).<br>
<br>
</span>Interestingly RISC-V claims immunity, and that looks like it'll be one of the <br>
two CPU architectures blessed by the Europeans in their Exascale project <br>
(along with ARM).<br>
<br>
<a href="https://riscv.org/2018/01/more-secure-world-risc-v-isa/" rel="noreferrer" target="_blank">https://riscv.org/2018/01/more<wbr>-secure-world-risc-v-isa/</a><br>
<br>
All the best,<br>
<div class="m_1077447318681479385HOEnZb"><div class="m_1077447318681479385h5">Chris<br>
-- <br>
Chris Samuel : <a href="http://www.csamuel.org/" rel="noreferrer" target="_blank">http://www.csamuel.org/</a> : Melbourne, VIC<br>
<br>
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