<div dir="ltr">Hi Chris,<div><br></div><div>They say that no announced silicon is vulnerable. Your link makes it clear that no ISA is immune if the implementation performs speculative execution. I think your point about two lines of production may make sense. Vendors will have to assess vulnerabilities and the performance trade-off.</div><div><br></div><div>Personally, I do not see a large HPC system being built out of non-speculative hardware. You would need much more hardware to reach a level of performance and the additional power could lead to a lower performance per Watt (i.e., exceed the facility's power budget).</div><div><br></div><div>Scott</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jul 17, 2018 at 2:33 AM, Chris Samuel <span dir="ltr"><<a href="mailto:chris@csamuel.org" target="_blank">chris@csamuel.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">On Tuesday, 17 July 2018 11:08:42 AM AEST Chris Samuel wrote:<br>
<br>
> Currently these new vulnerabilities are demonstrated on Intel & ARM, it will<br>
> be interesting to see if AMD is also vulnerable (I would guess so).<br>
<br>
</span>Interestingly RISC-V claims immunity, and that looks like it'll be one of the <br>
two CPU architectures blessed by the Europeans in their Exascale project <br>
(along with ARM).<br>
<br>
<a href="https://riscv.org/2018/01/more-secure-world-risc-v-isa/" rel="noreferrer" target="_blank">https://riscv.org/2018/01/<wbr>more-secure-world-risc-v-isa/</a><br>
<br>
All the best,<br>
<div class="HOEnZb"><div class="h5">Chris<br>
-- <br>
Chris Samuel : <a href="http://www.csamuel.org/" rel="noreferrer" target="_blank">http://www.csamuel.org/</a> : Melbourne, VIC<br>
<br>
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