<html>
<head>
<meta content="text/html; charset=utf-8" http-equiv="Content-Type">
</head>
<body bgcolor="#FFFFFF" text="#000000">
Nicole, <br>
<br>
Thanks for the reply. I figured that was the case. Just for the
record, I wasn't criticizing you, I was criticizing Intel/Micron for
not providing them. New technology is great, but how it's
performance compares to existing products is really the most
important information. <br>
<pre class="moz-signature" cols="72">Prentice Bisbal
Systems Programmer/Administrator
Office of Instructional and Research Technology
Rutgers University
<a class="moz-txt-link-freetext" href="http://oirt.rutgers.edu">http://oirt.rutgers.edu</a></pre>
<div class="moz-cite-prefix">On 07/29/2015 10:53 AM, Nicole Hemsoth
wrote:<br>
</div>
<blockquote
cite="mid:CACpHFbT836QXT6Dp-aarJYG43VmVNDd36OH2o_sV7Pb9hacACg@mail.gmail.com"
type="cite">
<div dir="ltr">Prentice,
<div><br>
</div>
<div>If they had been able to give a single metric or estimate
we would have published it. There are frustratingly few
details here. At all. But we will keep digging.</div>
</div>
<div class="gmail_extra"><br>
<div class="gmail_quote">On Wed, Jul 29, 2015 at 10:44 AM,
Prentice Bisbal <span dir="ltr"><<a moz-do-not-send="true"
href="mailto:prentice.bisbal@rutgers.edu" target="_blank">prentice.bisbal@rutgers.edu</a>></span>
wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex"><span
class="">On 07/29/2015 09:19 AM, Douglas Eadline wrote:<br>
</span>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex"><span
class="">
<br>
This could change a few things, non-transistor memory.<br>
<br>
"An Intel spokesperson categorically denied that it was
a phase-change<br>
memory process or a memristor technology. Spin-transfer
torque was also<br>
dismissed. Whatever it is, Intel and Micron have been
developing it for<br>
about ten years, and together as a joint venture since
2012."<br>
<br>
</span><a moz-do-not-send="true"
href="http://www.theplatform.net/2015/07/28/what-a-new-class-of-memory-means-for-the-future-applications/"
rel="noreferrer" target="_blank">http://www.theplatform.net/2015/07/28/what-a-new-class-of-memory-means-for-the-future-applications/</a><br>
<br>
</blockquote>
<br>
Did I miss something, or were performance metrics (or at
least estimates) completely missing from this article? The
one graphics says the cells can switch states 1000x faster
than NAND, but what does that mean for a complete package,
after all the other memory components are in the picture
(bus, controller, etc)?<br>
<br>
--<br>
Prentice<br>
_______________________________________________<br>
Beowulf mailing list, <a moz-do-not-send="true"
href="mailto:Beowulf@beowulf.org" target="_blank">Beowulf@beowulf.org</a>
sponsored by Penguin Computing<br>
To change your subscription (digest mode or unsubscribe)
visit <a moz-do-not-send="true"
href="http://www.beowulf.org/mailman/listinfo/beowulf"
rel="noreferrer" target="_blank">http://www.beowulf.org/mailman/listinfo/beowulf</a><br>
</blockquote>
</div>
<br>
<br clear="all">
<div><br>
</div>
-- <br>
<div class="gmail_signature">
<div dir="ltr">
<div>
<div dir="ltr">
<div>Nicole Hemsoth<br>
Co-Editor, <a moz-do-not-send="true"
href="http://www.theplatform.net" target="_blank">The
Platform</a><br>
</div>
919.899.9614<br>
</div>
</div>
</div>
</div>
</div>
</blockquote>
<br>
</body>
</html>