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<TITLE>RE: [Beowulf] Rackable / SGI</TITLE>
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From: <a href="beowulf-bounces@beowulf.org">beowulf-bounces@beowulf.org</a> [<a href="beowulf-bounces@beowulf.org">beowulf-bounces@beowulf.org</a>] On Behalf Of Greg Lindahl [<a href="lindahl@pbm.com">lindahl@pbm.com</a>]<BR>
Sent: Friday, April 03, 2009 4:32 PM<BR>
To: <a href="beowulf@beowulf.org">beowulf@beowulf.org</a><BR>
Subject: Re: [Beowulf] Rackable / SGI<BR>
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On Fri, Apr 03, 2009 at 08:47:42AM +0200, Eugen Leitl wrote:<BR>
> On Fri, Apr 03, 2009 at 07:34:26AM +0800, Stuart Midgley wrote:<BR>
><BR>
> > In 2019 when Intel releases their 1024core chip, still at 2.5GHz with<BR>
> > 256GB dimm memory, a lot of people will be surprised that linux works<BR>
><BR>
> Ain't going to work. Arguably doesn't work already beyond 8 cores<BR>
> in a single socket.<BR>
><BR>
> Will have to do with embedded memory or stacked 3d memory a la<BR>
> <a href="http://www.cc.gatech.edu/~loh/Papers/isca2008-3Ddram.pdf">http://www.cc.gatech.edu/~loh/Papers/isca2008-3Ddram.pdf</a><BR>
<BR>
We've been building bigger and bigger SMPs for a long time, making<BR>
changes to improve the memory system as needed. How is multicore any<BR>
different?<BR>
<BR>
memory bandwidth? The number of cores on a single CPU is growing much faster than the memory bandwidth to that CPU, right?<BR>
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