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At 10:54 AM 6/19/2006, Greg Lindahl wrote:<br>
<blockquote type=cite class=cite cite="">On Mon, Jun 19, 2006 at
06:02:45AM -0700, Jim Lux wrote:<br><br>
> Bear in mind, though, <br>
> that the processor itself is probably pretty susceptible to SEU, and
<br>
> doesn't have ECC internally.<br><br>
Processor *caches* do have ECC, and since they're more susceptible<br>
than the logic, this gets most of the benefit.</blockquote><br>
Some caches do, some don't. And it's tough to find out exactly what
they mean by ECC. A bit of searching on Intel's website turned up
this: <br>
<b><a name="cache26xx"></a>Integrated 2MB Level 2 Cache on IntelŪ
PentiumŪ 4 Processor Extreme Edition 3.73 GHz and 6xx<br>
</b>The 2-MB Advanced Transfer Cache (on-die, full-speed Level 2 cache)
with 8-way associative and Error Correcting Code (ECC) can improve
overall performance by allowing the processor to have faster access to a
larger amount of the most often used data.<br><br>
But I haven't been able to find out any more details.<br><br>
<br><br>
<blockquote type=cite class=cite cite=""> And some peripheral<br>
makers use ECC on all the rams in their chips, QLogic's
FiberChannel<br>
HBAs are an example.</blockquote><br><br>
yes.. but, for instance, do they do writeback and/or scrubbing when a
single bit error is detected, or do they just trust that by the time the
error occurs again in the same word, that you'll have written new
data?<br><br>
<br><br>
<blockquote type=cite class=cite cite="">-- greg<br><br>
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</blockquote>
<x-sigsep><p></x-sigsep>
James Lux, P.E.<br>
Spacecraft Radio Frequency Subsystems Group<br>
Flight Communications Systems Section<br>
Jet Propulsion Laboratory, Mail Stop 161-213<br>
4800 Oak Grove Drive<br>
Pasadena CA 91109<br>
tel: (818)354-2075<br>
fax: (818)393-6875<br>
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