[Beowulf] Power calculations , double precision, ECC and power of APU's

Geoffrey Jacobs gdjacobs at gmail.com
Fri Mar 22 14:10:55 PDT 2013


On 03/22/2013 03:09 PM, Vincent Diepeveen wrote:
> 
> On Mar 22, 2013, at 3:55 PM, Geoffrey Jacobs wrote:
> 
>> On 03/22/2013 09:42 AM, Vincent Diepeveen wrote:
>>>
>>> Suddenly only single precision without ECC is interesting. First time
>>> in history i've see anyone on this list care for that.
>>> Past decades only double precision with ECC mattered. Single
>>> precision overclocked and missing bits as always as all those
>>> gpu's do because of total overheating, was only for the gamer kids
>>> who fry every few months a videocard so to speak,
>>> because of too high of an overclock.
>>>
>>> Now intel releases a built in gpu line which obviously has no ECC
>>> inside the gpu and i doubt it has any double precision
>>> significance, and then suddenly only single precision without ECC is
>>> interesting.
>> No ECC might be an issue. Public information states approximately 2 SP
>> ops per DP op. Sounds like the SIMD registers can do both, like a normal
>> x86 chip.
> 
> For graphics registers of a built in GPU at a cpu they're gonna sell to
> kids gaming?
>
> I would be very amazed if it can do double precision at all.
> 
> AMD and Nvidia do or intend to do that  for the cheapest gamers cards as
> well.
> It just can hardly do double precision. The 2 for 1 ratio is a theoretic
> number that practical needs to be
> tested and only the highend versions might have enabled those transistors.

Speaking specifically about the Xeon Phi, that's what their quoted
numbers are. In the particular case of Radeon hardware, DP was quite a
bit slower because of the organization of the architecture going all the
way back to the R600. I don't have the information on hand to comment
about Radeon GCN or Nvidia architectures.

> Adding ECC to a GPU is a major problem and really not something that you
> 'just add'.
> It has huge bandwidth implications, especially limitations, i understood
> from a knowledeable hardware engineer
> whose name shall not be quoted and who for sure doesn't speak for any
> known manufacturer
> and sure not when talking to me.

It costs a lot of money to respin an ASIC to include pathways for parity
bits, scrub logic, etc. The performance costs are not phenomenal.

>> I'm not the biggest Intel fan, but untruths and deception don't add to
>> the dialog on this list.
>>
> 
> If you want to run double precision matrix calculations, just test that
> at it and get horrified...

I can't comment because I don't have an Intel Phi board. Neither do you.
Intel has published some numbers which indicate a performance penalty
similar to modern CPUs equipped with SIMD registers. Others on this list
should be able to provide validation or refutation of the data.

>>> A dutch saying is: "whose bread you eat his word you speak"
>>>
>>> That's the only relevant saying here and nothing else.
>>>
>>> On Mar 21, 2013, at 5:45 PM, Lux, Jim (337C) wrote:
>>>
>>>> The beard must have grey in it.
>>>>
>>>> Jim Lux
>> <snip>
> 



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