[Beowulf] Nehalem and Shanghai code performance for our rzf example
bill at cse.ucdavis.edu
Mon Jan 19 10:31:58 PST 2009
John Hearns wrote:
> BTW, re the discussion on processor frequency scaling,
> what finally did happen to Emitter Coupled Logic and gallium arsenide?
I followed the exponential "intel killer" for quite some time, although it
seemed obvious to me from the first slides it was going to be a failure. Sky
high clock rates, tiny caches, and a poor memory buss seemed to be destined
If gallium arsenide or some other material gave us 10x the clock rate per
watt, but 1/2 the transistors would it really matter? Seemed like even intel
is begrudgingly admitting it's the memory bus, and finally the nehalem is
blessed with dramatically more bandwidth.
Seems like increasingly cores are turning latency limited workloads (for the
parallel jobs of course) into bandwidth limited ones. Without a memory bus
that allows for 10x the bandwidth it doesn't really seem like 10x the clock
rate would be of particular use.
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