[Beowulf] Rackable / SGI
Nifty Tom Mitchell
niftyompi at niftyegg.com
Sat Apr 4 15:38:57 PDT 2009
On Sat, Apr 04, 2009 at 12:19:02PM -0700, Greg Lindahl wrote:
> On Sat, Apr 04, 2009 at 04:06:22PM +0200, Eugen Leitl wrote:
> > On Fri, Apr 03, 2009 at 01:32:13PM -0700, Greg Lindahl wrote:
> > > > Will have to do with embedded memory or stacked 3d memory a la
> > > > http://www.cc.gatech.edu/~loh/Papers/isca2008-3Ddram.pdf
> > >
> > > We've been building bigger and bigger SMPs for a long time, making
> > > changes to improve the memory system as needed. How is multicore any
> > Off-die memory bandwidth and latency are limited, so many codes
> > start running into memory bottlenecks even at moderate number
> > of cores
> Exactly like shared-bus multiprocessors.
> The incremental method of solving this is what Opteron/Nehalem does.
> The more radical method is what Origin/Altiax did. It all comes down to
> how many pins you're willing to commit to memory and how few pins you
> can squeeze a memory bus down to; ounce you bump up against that limit,
> then you need an improvement in packaging, which is no more radical
> than what Opteron/Nehalem or Origin/Altix did. And, of course, all
> this was invented before Opteron or Origin.
The memory bus issue is a serious issue but with a kilo-core chip
one solution may surface with a reflection back to the Inmos Transputer.
If there was core to core pipe like bus perhaps with a switch (not a
full blown any to any cross bar) that lets one core communicate via a
pipe equivalent to one or more cores. The pipe need not be too deep.
Perhaps 128 cache line equivalents. I do not think that it will be
necessary for each core to connect to all the other cores directly as
long as data could flow across the die. The interesting challenge for
coding would be to take advantage of a data flow across the die.
Two of the problems with the Transputer was the lack of virtual memory
and that the the network was fixed.
T o m M i t c h e l l
Found me a new hat, now what?
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